DDR Synchronous Dynamic Random Access Memories (DDR SDRAMs) are known. A DDR SDRAM is a type of volatile memory that is extensively used as system memory for the computers, for example for the Personal Computers (PC).
Unlike other types of random access memories, a SDRAM memory is provided with a synchronous interface. Thus, the SDRAM memory requires the presence of a clock signal that is used for driving a finite state machine for timing the instructions received at control inputs of the memory. Thanks to this timing, an SDRAM memory is capable of managing operations that are more complex compared to those manageable by means of non-synchronous random access memories, such as a dynamic random access memory (DRAM).
The SDRAM memories are further characterized by having a high potential access band because each reading operation may interest several thousands of information bits.
For further improving the performances offered by such a memory type, a Double Data Rate (DDR) interface has been developed. Thanks to the presence of the double rate interface, the memory is capable of executing two reading or writing transfers for each cycle of the clock signal (particularly, one in correspondence of the rising fronts of the clock signal, and one in correspondence of the falling fronts). Compared to the other SDRAM memories, the minimum read/write unit (i.e., the minimum quantity of data that is read/written during an access to the memory) is doubled: in a DDR SDRAM memory, each single access refers to at least two consecutive memory words. This technique allows the doubling of the transfer speed of the data without having to increase the working frequency of the memory bus. In other words, the clock signal of a DDR SDRAM is exploited more with respect to the case of a single rate SDRAM memory, because the “real” transfer frequency is twice the clock frequency.
As it is known to the skilled technicians, the Joint Electron Device Engineering Council (JEDEC) has established standards regarding the characteristics and the specifics of the DDR SDRAMs. Moreover, the JEDEC has provided several specific protocols for the management of the operations required for the use and operation of such memories.
Seeing the numerous advantageous characteristics of the DDR SDRAM memories, it would be desirable to have a non-volatile counterpart thereof (capable of maintaining the information even in absence of an electrical supply), i.e., a Non-Volatile DDR Memory (DDR NVM), to be coupled thereto. In this way, it would be possible to have performances comparable to that offered by the DDR SDRAM memories in all those application fields that require the saving of the information in a permanent way, but that, at the same time, require short response times. Moreover, in certain applications in which the available resources, intended as both available power and available silicon area within the chip integrating the memories, are limited, it would be highly desirable that the DDR SDRAM memories and the DDR NVM memories use the same interfaces and the same communication buses as much as possible. For example, in order to increment the speed performances of mobile terminals for telecommunications, it would be advantageous to substitute the non-volatile memories of the classic type used for storing data with DDR NVM memories, reducing the access times to the memory.
A substantial difference occurring between the non-volatile memories and the volatile memories consists in the different way the data are written (program phase). Particularly, the program phase of a non-volatile memory is usually more complex and requires a higher amount of time. For example, in order to program a flash non-volatile memory it is necessary to apply a series of (voltage or current) pulses to the memory cells to be programmed, and, after the application of each pulse, the programming state of the memory cells is usually verified. This requires a greater amount of time compared to that necessary for programming the same quantity of data in a volatile memory.
Because of the major difference occurring between the DDR NVM memories and the DDR SDRAM memories, it would be thus necessary to differentiate the communication buses and at the same time follow protocols for the management of the operations that are greatly different to each others. However, such a solution is expensive in terms of resources, and thus not optimized to be implemented for mobile terminals for telecommunication devices (and in general for the devices having limited resources).